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Autonomous Vehicles

PCI Express® Cruises the Automotive Fast Lane

June 30, 2021

According to market analysts, the autonomous car market will rise from $20.97 billion in 2020 to $61.93 billion in 2026, for a CAGR of 22.75%, during the five-year timeframe.1 Given this expected growth rate, verifying advanced driver-assistance systems (ADAS) will take on greater importance.

ADAS is also one reason PCIe® architecture is expanding rapidly in automotive designs. With the latest PCIe generation – 6.0 – the use of the technology will only become more prominent, especially in autonomous vehicles.

Why is PCIe racing to the interconnect lead in advanced vehicle designs? Three main reasons:

Bandwidth – The latest PCIe 6.0 specification increases bandwidth to 64 GT/sec. PCI-SIG® is committed to continuing the bandwidth doubling shown in Figure 1 in future specifications, allowing it to support emerging automotive technologies.

PCIe data rates by generation.
Figure 1: PCIe data rates by generation.

ConnectivityPCIe hardware guarantees data packets will be transferred to the desired destination, unlike other interconnects that rely on software. Plus, PCIe has much lower latency capabilities than alternatives such as Ethernet.

Ecosystem – There is plenty of off-the-shelf silicon that utilizes PCIe technology, ranging from Wi-Fi chipsets to 5G modems. This field-proven track record includes infotainment and navigation systems used in connected cars.

Overcoming the Complexity Roadblock

The doubling of data rates and other performance upgrades of PCIe 6.0 adds complexity to high-speed interconnects used in automotive designs. Engineers need signal integrity tests and analysis tools to verify products comply with PCIe 6.0 standards.

PCIe 6.0 utilizes 32 Gbaud PAM4 signaling. Though the underlying frequency is the same as the PCIe 5.0 specification, there is extra circuitry and logic involved for PAM4 to track three eyes, along with the logic changes to operate in Flow Control Unit (FLIT) mode. Because error correction happens on FLIT, cyclic redundancy check (CRC) and retry must take place at the FLIT level.

Because PCIe 6.0 has three eyes in the same UI, eye height and width are reduced. BER will be several levels of magnitude higher with PAM4 as a result, which is why Forward Error Correction (FEC) is necessary.

FEC Importance

PCI-SIG established a low-latency FEC of <2 nsec for PCIe 6.0, and it will be part of the specified overall signal latency of <10 nsec. FEC is based on a fixed number of symbols, making it simple to transition to FLITs, as they are fixed size, as well.

FEC logic is expected to operate at 1G (or 500 MHz or 2G) and easily reach a latency exceeding 2 nsec. PCI-SIG recommends a lightweight FEC for correction. The robust CRC for detection, combined with a fast link-level replay, handles any errors that the FEC cannot correct. As long as the replay probability of a FLIT is approximately 10-6, there is no appreciable performance impact either from the FEC latency or the replay latency in case of an undetected error.

A recommended approach is to establish a FEC symbol error threshold. To set a threshold, a bit error rate tester (BERT) generates a PAM4 signal to the Device Under Test (DUT) receiver input. The DUT determines the logic state of the input signal and loop decision to transmitter output for the error signal in the BERT for analysis. The BERT’s built-in Error Detector (ED) determines if the DUT’s decision was correct. For relevant results, the BERT’s jitter and noise profiles must comply with standards.

Link Equalization Factors

Link training and stressed receiver tolerance are simultaneously evaluated using a stressed signal in the link equalization test. Tests for receivers and transmitters must take place using SigTest software developed by the PCI-SIG.

Receiver link equalization testing (figure 2) has one notable difference from a standard stressed-eye receiver BER. The DUT must first perform link negotiation to correctly compensate for the test channel. The idea of stressed receiver tolerance testing is to send the DUT-receiver the worst-case signal that still complies with the specification.

Receiver link equalization test configuration.
Figure 2: Receiver link equalization test configuration.

Prior to conducting the test, the signal transmitted from the BERT must be precisely calibrated to generate the worst-case signal at the end of the test channel. The test signal has jitter and interference impairments that include random jitter (RJ), sinusoidal jitter (SJ), sinusoidal differential mode interference (DMI), and common mode interference (CMI) through loss channel intersymbol interference (ISI).

Transmitter link equalization testing (figure 3) is a required compliance test that verifies the device correctly changes equalization within the specified time when the link partner requests it. The BERT requests an equalization change from the devices that simultaneously sends a trigger to an oscilloscope, so the time delay to the DUT can be measured in the electrical domain.

Transmitter link equalization test setup.
Figure 3: Transmitter link equalization test setup.

Selecting Proper Test System

To conduct these measurements accurately, PCIe 6.0 test systems need a feature-rich, protocol-aware BERT, along with an oscilloscope. The BERT needs a built-in instrument-quality Pulse Pattern Generator (PPG) that can apply precise levels of specific signal impairments and a built-in ED capable of verifying compliance with the PCIe specifications. The BERT should have multiple NRZ pattern-generating channels and error detectors that operate at 32 GT/sec and PAM4 channels at 64 GT/sec to support PCIe 6.0 and earlier generations.

Low intrinsic jitter of 115 fsec and 12 psec 20 to 80% rise/fall times are also necessary for signal integrity. The BERT must apply every required signal impairment in amplitude ranges that exceed those required by the PCIe 6.0 specifications,

The built-in ED of the Signal Quality Analyzer-R MP1900A has FEC analysis functions to detect FEC symbol errors based on the 400 GbE FEC standard. Bit error changes and FEC symbol errors with alterations in input amplitude and jitter conditions can be monitored in real-time to quickly and reproducibly conduct evaluations when symbol error counts exceed the correction ability of FEC.

You can learn more about PCIe 6.0 and how to solve associated testing challenges by downloading an application note on the topic. For advanced automotive design solutions, you can also download a TU Automotive e-book.

Source:
1 Autonomous/Driverless Car Market – Growth, Trends, COVID-19 Impact, and Forecast (2021 - 2026); Mordor Intelligence