January 16, 2014
As the New Year kicks into full swing, attention turns to DesignCon 2014. Chip, board and systems design engineers in the high-speed communications and semiconductor communities will convene in Santa Clara from January 28-31 and walk the aisles of the Santa Clara Convention Center to learn the latest theories, methodologies, applications and advanced design tools.
Anritsu will be exhibiting in booth #501 and will show test solutions that accurately test high-speed signals. Among the instruments on display will be our VectorStar™ MS4640B Vector Network Analyzer (VNA), which will be the star of several VNA-related activities at DesignCon.
Several Technical Sessions
On Wednesday, January 29th, Anritsu will sponsor a day of technical sessions. Amongst which will be one at 3:35 PM entitled The Role of Improved Measurements and Tools in Assessing Simulation-Measurement Correspondence for 32 Gbps Systems. This session, which I co-authored with Alfred Neves of Wild River Technology, will look at the use of S-parameter measurements for high-speed serial designs. It will highlight various considerations, including the importance of the extent of the frequency range at low- and high-end of S-parameter measurements and how this affects achieving correlation between simulation and measurement. The use of various tools will be described, including VNAs, channel modeling platforms and BERTS, and how they fit into the high-speed serial data interconnect design flow. All of the sponsored technical sessions will be given in Mission City Ballroom M2.
Secondly, Anritsu and Wild River Technology will present a joint paper entitled Managing S-Parameter Data for 10 to 32 GB/S Time-Domain Simulations in Ballroom K from 11:05-11:45 AM during the main technical conference. The paper is co-authored by Jon Martens and me from Anritsu, as well as Al Neves and James Bell from Wild River Technology. To whet your appetite, here is the abstract:
The traditional S-parameter model approach for high-speed time domain simulations does not always work well. This can result in time domain distortion and poor estimation of peak-peak deterministic jitter, vertical eye diagram fidelity and contour due to a lack of causality, and poor DC point estimation. This session will be valuable to engineers designing systems from 10 to 32 Gb/s, and system and 3D EM simulator users. It refocuses the RF/Microwave centrism of VNA-produced S-parameter data to a sampled system construct which is then extrapolated down to DC and up to frequencies higher than initially measured. An explanation will be given of how the discrete frequency sampled nature of the S-parameter measurement affects time domain simulation. Finally, practical measurement results will be presented to illustrate how the sampled-model impacts various structures and how the uncertainties vary depending on the selected start frequency, stop frequency, and point density.
Live Booth VNA Demonstrations
Providing live action in the booth, the VectorStar MS4640B will be showcased on two stations. One will show the advanced VNA system making measurements on the Wild River Technology Channel Modeling Platform. Both products are critical to verify simulation-measurement correspondence. A second station will show VectorStar with its internal second source and DifferentialView™ options making true mode stimulus mode measurements on a differential amplifier.
I hope you can make it to DesignCon. If you do, please visit our booth and introduce yourself; it’s always good to meet blog readers in person.
You can learn more about the conference and show by visiting the DesignCon website. To read about other signal integrity design challenges and how VNAs can help conduct high-speed measurements, you can download a white paper.
